1. Field of the Invention
The present invention relates generally to a semiconductor process, and more particularly, to a silicon substrate and a chip package structure formed by applying said semiconductor process.
2. Description of Related Art
With advance of semiconductor technologies at present, integrated circuit (IC) chips are equipped with a great number of closely arranged transistors and a plurality of signal pads disposed on surfaces of chips. The chips, for the purpose of packaging, are often disposed on a chip package carrier, so as to form a chip package structure. Here, by applying a package process, sufficient signal paths, heat dissipating paths, and structural protection can be supplied to the chips.
At this current stage, the package technology is progressing, and various chip package structures have been continuously developed. For instance, a chip is adhered to inner leads of a lead frame or a die pad to form a thin small outline package (TSOP). Alternatively, a chip is adhered to a printed circuit board to form a ball grid array (BGA) package.
In the TSOP structure, the chip is adhered to the inner leads of the lead frame or the die pad, and a plurality of outer leads for electrically connecting external devices are disposed at edges of the TSOP structure. Since the outer leads are uncovered by a molding compound, it is likely for the outer leads to be affected by external surroundings or broken due to excessive lengths of the outer leads, which further poses an impact on signal transmission.
On the other hand, in the BGA package structure, an organic substrate or a ceramic substrate often serves as a carrier of the chip, and the chip is disposed behind the carrier, such that electrical signals of the chip can be routed downward to a bottom surface of the carrier through internal circuits of the carrier, and the routed electrical signals can be finally transmitted to external electronic devices through solder balls of the carrier. Since the solder balls are formed on the bottom surface of the carrier in an area array manner, the aforesaid BGA package structure is frequently used in a high pin count semiconductor device. Nonetheless, an entire height of the BGA package structure is approximately 1.0˜1.4 mm, which is not compliant with the demands on miniaturization (i.e., the height is smaller than 0.5 mm).